In this module we will study automatic test pattern generation (ATPG) using sensitization–propagation -justification approach. We will first introduce the basics of. 1. VLSI Design Verification and Testing. Combinational ATPG Basics. Mohammad Tehranipoor. Electrical and Computer Engineering. University of Connecticut. Boolean level. • Classical ATPG algorithms reach their limits. ➢ There is a need for more efficient ATPG tools! 6. Circuits. • Basic gates. – AND, OR, EXOR, NOT.

Author: Arashigore Mijin
Country: Brazil
Language: English (Spanish)
Genre: Health and Food
Published (Last): 21 February 2004
Pages: 272
PDF File Size: 15.22 Mb
ePub File Size: 5.82 Mb
ISBN: 150-8-22847-753-7
Downloads: 59004
Price: Free* [*Free Regsitration Required]
Uploader: Shamuro

Automatic test pattern generation

In such a circuit, any single fault will be inherently undetectable. Second, it is possible that a detection pattern exists, but the algorithm cannot find one. A defect is an error caused in a device during the manufacturing process. The effectiveness of ATPG is measured by the number of modeled defects, or fault modelsdetectable and by the number of generated patterns.

Hence, if a circuit has n signal lines, there are potentially 2n stuck-at faults defined on the circuit, of which some can be viewed as being equivalent to others. A fault is said to be detected by a test pattern if the output of that test pattern, when testing a device that has only that one fault, is different than the expected output.

This page was last edited on 23 Novemberat As design trends move toward nanometer technology, new manufacture testing problems are emerging. Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit.

Testing very-large-scale integrated circuits with a high fault coverage is a difficult task because of complexity.

For designs that are sensitive to area or performance overhead, the solution afpg using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition.


Combinational ATPG Basics

In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. For nanometer technology, many current design validation problems are becoming manufacturing test problems as well, so new fault-modeling and ATPG techniques will be needed. However, these test generators, combined with low-overhead DFT techniques such as partial scanhave shown a certain degree of success in testing large designs.

By using this site, you agree to the Terms of Use and Privacy Policy.

The single stuck-at fault model is structural because it is defined based on a atpt gate-level circuit model. The ATPG process for a targeted fault consists of two phases: Sequential-circuit ATPG searches for a sequence of test vectors to detect a particular fault through the space of all possible test vector sequences.

Fault activation establishes a signal value at the fault model site that is opposite of the value produced by the fault model.

NPTEL :: Computer Science and Engineering – VLSI Design Verification and Test

These metrics generally indicate test quality higher with more fault detections and test application time higher with more patterns. Various search strategies and heuristics have been devised to find a shorter sequence, or to find a sequence faster. Removing equivalent faults from entire set of faults is called fault collapsing. ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test full scansynchronous sequential, or asynchronous sequentialthe level of abstraction used to represent the circuit under test gate, register-transfer, switchand the basica test quality.


The classic example of this is a redundant circuit, designed such that no single fault causes the output to change. Equivalent faults produce the same faulty behavior for all input patterns.

However, according basicw reported results, no single strategy or heuristic out-performs others for all applications or circuits.

A fault model is a mathematical description of how a defect alters design behavior.

A short circuit between two signal lines is called bridging faults. During design validation, engineers can no longer ignore the effects of crosstalk and power supply noise on reliability and performance.

Therefore, many different ATPG methods have been developed to address combinational and sequential circuits. ATPG is a topic that is covered by several conferences throughout the year.

Combinational ATPG Basics

The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern.

It is also called a permanent fault model because the faulty effect is assumed to be permanent, in at;g to intermittent faults which occur seemingly at random and transient faults which occur sporadically, perhaps depending on operating conditions e.

ATPG can fail to find a test for a particular fault in at least two cases. Any single fault from the set of equivalent faults can represent the whole set. If one driver dominates the other driver in a bridging situation, the dominant driver forces the logic to the other one, in such case a dominant bridging fault is used.